1. Field of the Invention
The present invention relates to techniques for communicating signals through switches. More specifically, the present invention relates to the design of a multi-chip switch comprised of semiconductor dies that communicate with each other using capacitively coupled proximity pads or connectors.
2. Related Art
Many computer systems and networks include switches to selectively communicate data items between different system components. These switches often include multiple input ports and multiple output ports, which are often implemented as high-speed serial input/output (I/O) ports. In contrast with lower-speed parallel ports, these high-speed serial ports offer advantages, such as a reduction in overall power consumption and in associated port area (in terms of the number of printed circuit boards, integrated circuit or chip packages, and/or I/O connectors). However, high-speed serial ports typically require additional circuits to serialize and deserialize data, to encode and decode data, and to recover an embedded clock. These additional circuits typically consume a significant amount of the area on an integrated circuit. These circuits, therefore, may partly determine the size and complexity of a chip.
Furthermore, many existing switches are based on the memory switch architecture illustrated in FIG. 1. A memory switch 110 includes a shared multiple-port memory that includes one or more logical buffer memories 114 that selectively couple input ports 112 to output ports 118 in accordance with a configuration provided by control logic 116. The shared memory switch 110 provides sufficient memory bandwidth that the input ports 112 can simultaneously write data into the buffer memories 114, thereby avoiding data collisions. Buffer memory 114 is typically high-bandwidth memory that is often implemented on-chip. The amount of buffer memory, therefore, may also determine the size of a switch.
If the scale of the switch does not allow for a single-chip implementation, the switch may have to be partitioned among several chips with each chip providing a fraction of the aggregate switching capacity. Such multiple-chip implementations are often based on architectures that include multiple switching stages or multiple switching planes.
Unfortunately, it is often challenging to provide interconnects in a multi-chip switch with an aggregate bandwidth that is sufficient to accommodate the total bandwidth of the signals received by the switch. As a consequence, interconnects in large-scale switches may be complicated and expensive. For example, existing switches that offer multiple Tb/s capability typically include multiple racks with cabling between the racks to provide interconnects that can accommodate the full bandwidth of the switch.
Therefore, multi-chip switches often have large footprints and consume significant amounts of power. Moreover, as the size of a given switch increases, it may be more difficult to control due to increased delays and latency. This, in turn, may lead to challenges associated with coordinating or scheduling the data flow in the switch. The complexity and expense associated with the components used to address these challenges can greatly impact the performance and reliability of multi-chip switches.
Hence, what is needed is a method and an apparatus that facilitates switching without the problems listed above.